1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly to a semiconductor memory device in which faulty cells causing standby current failure can be replaced with redundancy cells.
2. Description of the Prior Art
In general, standby current is regarded as a crucial factor in a low power semiconductor memory products, common to all portable information and communication devices, so that it should be taken into consideration in designing a semiconductor memory chip and a method has been required to replace faulty cells causing standby current failure with redundancy cells.
Particularly, if the standby current failure is caused by current leakage at supply voltage (Vcc) node, the possibility of repairing such faulty cells definitely depends on presence of a cell power repairing circuit to stop supply voltage (Vcc) from flowing to cells. Therefore, the presence of the cell power repairing circuit can exert a great deal of influence on the yield of products.
A semiconductor memory device of the prior art includes: cell power lines arranged between bit lines in an identical direction for providing supply voltage to cells of memory cell array; and cell power repairing circuits arranged at the periphery of the memory cells in the direction of word lines for blocking supply voltage from flowing to the cell power lines. Detecting a faulty cell causing standby current failure, a corresponding cell power repairing circuit stops supply voltage from flowing to a cell power line connected with the faulty cell, thereby enabling the faulty cell to be replaced with redundancy cells. The prior art about the cell power repairing circuits as such has been disclosed in Japanese patents Nos. Hei 10-199290 and Hei 05-314790.
In the prior art, the cell power lines have been arranged in an identical direction to bit lines to result in a large size of a chip. In consequence, it has been necessary to figure out a method to make a reduction in the size of a chip in order to keep up with a current trend of minimizing the size of a semiconductor memory device.
Therefore, it is an object of the present invention to provide a semiconductor memory device in which cell power lines are arranged in n identical direction to word lines and cell power repairing circuits are arranged between cell blocks of a memory cell array to thereby reduce the size of a chip.
It is another object of the present invention to provide an arrangement structure and method of cell power repairing circuits adequate for a high integration semiconductor memory device.
In order to accomplish the aforementioned object of the present invention, there is provided a semiconductor memory device including: a plurality of word lines, a plurality of bit lines, a plurality of cells connected between the word lines and bit lines for storing data and a memory cell array of a plurality of cell blocks having a plurality of cell power lines for providing supply voltage to the cells; a plurality of row decoder circuits for decoding external row addresses and generating selection signals for predetermined word lines of the cell blocks; and a plurality of cell power repairing circuits for selectively blocking between cell power lines which provide supply voltage to faulty cells and power source if there are any faulty cells causing standby current failure, wherein the cell power lines are arranged between the word lines in an identical direction; the row decoder circuits are respectively arranged between two neighboring cell blocks; and the cell power repairing circuits are also respectively arranged between cell blocks.
According to another aspect of the present invention, there are provided in a static random access memory device cell power repairing circuits to selectively block an electrical connection between power supply lines and cell power lines corresponding to any faulty memory cells in occurrences of standby current failure. At this time, the cell power repairing circuits are arranged in an identical direction of word lines between separate memory cell array blocks, and the fuses which actually construct the cell power repairing circuits are arranged in a predetermined length to the direction of word lines and extended to the direction of bit lines.